VIVADO DESIGN SUITE

IP AND SYSTEM-CENTRIC TOOL SUITE ACCELERATING PROGRAMMABLE SYSTEMS INTEGRATION AND IMPLEMENTATION BY UP TO 4X :

Programmable devices are at the heart of most systems today, enabling not only programmable logic design, but programmable systems integration. Xilinx has transformed from an FPGA company to an ‘All Programmable’ company, offering technology from logic and IO to SW programmable ARM® processing systems and beyond.With the next decade of programmable platforms, comes the next generation design environment that meets the aggressive pace and the need for enhanced productivity.

Xilinx introduces the Vivado™ Design Suite, an IP and system-centric design environment built from the ground up to accelerate productivity for the next generation of ‘All Programmable’ devices. The new Vivado Design Suite is already proven to accelerate integration and implementation by 4x over traditional design flows, reducing cost by simplifying design and automating, not dictating, a flexible design environment.

Vivado Design Suite provides a highly integrated design environment with a completely new generation of system-to-IC level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as AMBA® AXI4 interconnect, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys® Design Constraints (SDC) and others that facilitates customized design flows. Vivado was architected to enable the combination of all types of programmable technologies and scale up to 100M ASIC equivalent gate designs.

Accelerating Integration and Implementation To eliminate bottlenecks in integration, the Vivado Design Suite includes electronic system level (ESL) design for rapidly synthesizing and verifying C/C++/SystemC-based algorithmic IP, standards based packaging of both algorithmic and RTL IP for reuse, standards based IP stitching and systems integration of all types of IP, and the verification of blocks and systems with 3X faster simulation and HW Co-simulation provides 100X performance. 

The Vivado Design Suite accelerates the implementation process by enabling more turns per day and helping to eliminate them altogether. The new Vivado data model improves run times up to 4x compared to competing solutions. Vivado includes a hierarchical chip planner, a 3-15X faster logic synthesis tool with industry leading support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a ‘cost’ function of multiple variables such as timing, wire length and routing congestion. In addition, incremental flows allow for ECO (Engineering Change Order) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. Finally, leveraging the new shared scalable data model, power, timing and area estimates are provided at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.

Xilinx Solution Highlights

• Next generation of system-to-IC level tools, built on the backbone of a shared scalable          data model and a common debug environment

• 4x productivity advantage drives beyond programmable logic to programmable systems        integration

• ’All Programmable’ device support including 3D stacked silicon interconnect technology,        ARM processing systems and Analog Mixed Signal (AMS).

For More Info:

Name    : Vinay Kumar 
Email Id: vinaykmrgarg@gmail.com